The Thermal Time Constant and the 1800 s Trace: Why a GPU Thermal Test Runs for 30 Minutes

A GPU cooler is a large piece of metal, and metal takes time to heat. A benchmark that runs for a few minutes reports the temperature of a cooler that is still warming up. Every Assurd certificate is built on a thermal trace with 1800 seconds of sustained load. This post derives, from a simple model of the cooler, what a trace of a given length actually observes, and then defines the trace-wide figures the certificate takes from it: the peak effective clock, the peak VRAM temperature and the peak VRM temperature.

The procedure is SOP-GPU-001 v1.1, Step 3.2. Every figure below is computed by the Kairoscope backend from the uploaded HWiNFO log; none is typed in by a technician.

A first-order model of the cooler

Model the heatsink as one lump with thermal resistance $R_\theta$ to the room air (K/W) and heat capacity $C_\theta$ (J/K). Under a constant load it approaches its final temperature exponentially:

$$\begin{gathered} T(t) = T_a + \Delta T_{ss}\,\bigl(1 - e^{-t/\tau}\bigr), \\ \tau = R_\theta\,C_\theta , \end{gathered}$$

where $T_a$ is the ambient temperature, $\Delta T_{ss}$ is the steady-state rise above ambient, and $\tau$ is the thermal time constant. A cooler with more metal (larger $C_\theta$) or a weaker path to the air (larger $R_\theta$) takes longer to settle.

The useful quantity is the fraction of the final rise reached after $n$ time constants, $1 - e^{-n}$:

Time	Fraction of the rise reached
$0.5\,\tau$	0.3935
$1\,\tau$	0.6321
$1.5\,\tau$	0.7769
$2.5\,\tau$	0.9179
$3\,\tau$	0.9502
$5\,\tau$	0.9933

Three time constants is the usual engineering reading of "settled": 95% of the rise, with 5% still to come.

The model is deliberately simple. A real card has a die, a vapour chamber or heat pipes, fins and fans whose speed follows a curve, so its response is a sum of several exponentials rather than one. The single lump captures the slowest of them, the heatsink mass, and that is the one that sets how long a test must run.

What a short test sees

For a triple-fan heatsink, SOP Step 3.2 takes $\tau$ to be typically 600 to 1200 seconds. That range is an engineering estimate for the class of cooler; Assurd does not measure or certify $\tau$ for a given card. Take an illustrative cooler with $T_a = 22$ °C and $\Delta T_{ss} = 40$ °C and evaluate the model at the two ends of the range:

Load time	$\tau = 600$ s	$\tau = 1200$ s
300 s	37.7 °C	30.8 °C
1500 s	58.7 °C	50.5 °C
1800 s	60.0 °C	53.1 °C
steady state	62.0 °C	62.0 °C

At 300 s, the length of a typical benchmark loop, the faster cooler has covered 39% of its rise and the slower one 22%. Both read as comfortably cool. Neither number describes the card in sustained use.

At 1800 s the faster cooler is at $3\,\tau$, within 2.0 °C of steady state. The slower one is at $1.5\,\tau$: it has covered 78% of its rise and is still 8.9 °C short. Stated plainly, 1800 s reaches the 3τ point only for coolers at the fast end of the SOP's range. For slower coolers the final minutes of the trace are near equilibrium, not at it. The SOP sets 1800 s of load as a minimum, and the trace length is an engineering prior like every other threshold here.

Why the end of the trace still works

The figures that matter most do not need the heatsink to be fully settled.

The hotspot delta is a difference between two die sensors. In the lumped model the heatsink temperature adds to both equally and cancels; what remains is set by the heat flow through the die and its thermal interface, and under a fixed load that flow is steady long before the heatsink mass is. The steady-state window, the inclusive span 1500 s ≤ t ≤ 1800 s, is the last five minutes of the trace, as far from the start-up transient as the trace goes.

The window also bounds how much the heatsink can still drift while it is being averaged. In the example above, the faster cooler moves 1.3 °C across the window and the slower one 2.5 °C: a slope, but a small one beside the start of the trace, where the same cooler climbs by tens of degrees.

Two more effects only appear late in a long trace, which is the other reason the SOP gives for the length. Fan bearing wear shows up as RPM instability at the settled fan speeds the cooler reaches once it is hot (the SOP checks the RPM standard deviation over the last 60 s at each setpoint against 35 RPM). And thermally activated faults in the power delivery need the board to be hot before they show at all.

Finding the start of load

All Phase 3 times are load-relative: $t = 0$ is the detected load start, not the first line of the HWiNFO log. The log begins with a 120 s idle pre-conditioning period, and the operator does not start the stress test at an exact second, so the backend finds the start itself:

• The log is resampled to 1 s bins. Bins with no utilization reading are skipped, not counted as idle.
• Load start is the first second at which GPU core utilization exceeds 50% and stays above it for at least 10 s, with no gap between utilization readings longer than 5 s.
• Every sample before load start, including the idle period, is dropped from the stored series. Nothing is kept at negative time.
• The trace is cut at 1800 s of load. The stored duration is the last sample's time plus one logging interval, as parsed by the server; the technician cannot edit it.

For example: the idle period ends, utilization jumps above 50% for six seconds while the benchmark loads, falls back, and then climbs above 50% for good at log second 131. The six-second burst is not load start, because it does not last 10 s. Log second 131 becomes $t = 0$, and the steady-state window is log seconds 1631 to 1931.

Two outcomes are blocking validations rather than findings. A log in which no sustained load is ever detected is rejected at upload. A trace with less than 1800 s of load is refused as "Trace shorter than 1800 s of load — re-run per SOP 3.2". Neither can be overridden by a justification, and neither quarantines the card: the technician runs the trace again.

Peak effective clock

The peak effective clock is the highest effective core clock in the trace:

$$f_{\text{peak}} = \max_{0 \le t \le 1800\ \text{s}} f_{\text{effective}}(t) .$$

"Effective" means the clock the shader cores actually ran at, averaged over each sample, rather than the requested boost target. The maximum is taken over the 1 s samples of the whole load-relative trace; the idle pre-conditioning is excluded. A boost algorithm usually reaches its highest clock while the card is still cool, so the peak is a statement about the card's boost ceiling, not about the clock it holds once warm. The certificate ranks it as the sustained-boost metric within its cohort, and it also feeds the unitless clock/power index.

Peak VRAM temperature

The peak VRAM temperature is the highest memory-junction temperature in the trace:

$$T_{\text{VRAM}} = \max_{0 \le t \le 1800\ \text{s}} T_{\text{mem}}(t) .$$

It is the junction reading the card reports for its memory, where the card exposes one, taken over the same samples. Memory packages sit on the board around the die and are cooled through thermal pads to the cooler or backplate, a slower and less direct path than the die's, so their peak tends to arrive late in a long trace. A short test is especially blind to it.

Peak VRM temperature

The peak VRM temperature is the highest voltage-regulator temperature in the trace:

$$T_{\text{VRM}} = \max_{0 \le t \le 1800\ \text{s}} T_{\text{vrm}}(t) .$$

Many cards have no VRM temperature sensor at all. For those, the reading is absent in every sample and the peak is null; the certificate shows it as not measured. It is never estimated from the core temperature, defaulted to 0, or interpolated. The thermal image taken inside the steady-state window carries a spot reading behind the VRM phases on every certificate minted since the image became required, but that image is disclosure evidence, read off the backplate by a camera; it is not a substitute for the sensor and is never written into this field.

Rules for every trace-wide figure

The three peaks share a set of rules:

• 1 s samples. HWiNFO logs every 1000 ms; the parser resamples to 1 s bins and each peak is the maximum over those samples.
• Load-relative. Only samples from $t = 0$ to $t = 1800$ s count. The idle pre-conditioning never sets a peak.
• Absent stays absent. A sensor the card does not expose is null in every sample, and a peak over no readings is null, never 0.
• Rounding. Peaks are stored to 0.1 and shown on the certificate to whole MHz or °C.

The trace's other steady-state figure, the average board power, follows the hotspot delta's rule: the mean of the hardware power monitor's readings over 1500–1800 s, null for a short trace or an empty window. Peak board power is the maximum over the full 1800 s.

Calibration status

Every threshold in this post is an engineering prior pending fleet calibration (n ≈ 300): the 1800 s trace length, the 1500–1800 s window, the 50% / 10 s / 5 s load-start rule, the 600–1200 s range for $\tau$ and the 35 RPM fan limit. They follow from the model above, not from a fitted population, and we do not describe them as empirical or statistically validated. Once the fleet holds roughly 300 certified cards, they will be reviewed against the observed traces, and any change will be versioned in the SOP.

The definitions themselves, load-relative time, maxima over the samples that exist and null for a sensor that does not, are not priors. They are arithmetic, and they will not change with calibration.

See it on a certificate

The sample certificate shows the thermal trace and these peaks as they appear on an Assurd certificate. Its numbers are illustrative: they come from synthetic logs run through the production parser, not from a measured card.

Notation

Symbol	Meaning	Unit
$t$	Time since detected load start	s
$T_a$	Ambient temperature	°C
$\Delta T_{ss}$	Steady-state rise above ambient	K
$R_\theta$, $C_\theta$	Heatsink thermal resistance and heat capacity	K/W, J/K
$\tau$	Thermal time constant, $R_\theta C_\theta$	s
$f_{\text{peak}}$	Peak effective core clock over the trace	MHz
$T_{\text{VRAM}}$	Peak memory-junction temperature over the trace	°C
$T_{\text{VRM}}$	Peak voltage-regulator temperature (null without sensor)	°C