Silicon DNA: The Physics of Clock States, Voltage and the V/F Curve

A GPU's clock speed and supply voltage are not independent settings. Every chip has a voltage-frequency (V/F) curve: for each operating frequency, the minimum voltage at which the chip runs reliably. The card's firmware and boost algorithm work along that curve all the time, trading clock speed against power, temperature and voltage limits.

This post explains the physics behind that curve: why voltage and frequency are coupled, why two chips of the same model sit on different curves, how heat and current slowly wear out a chip's wiring, and how the voltage regulator delivers the current. It ends with what an Assurd certificate records about clocks and power, and what it does not.

The physics of switching

The CMOS switching model

GPU logic is built from CMOS transistors: complementary pairs of PMOS and NMOS transistors that switch each node between the supply voltage $V_{DD}$ and ground. Every switch charges or discharges a small capacitance, and that costs energy. The dynamic power of the chip is

$$P_{\text{dyn}} = \alpha\, C_L\, V_{DD}^2\, f ,$$

where:

• $\alpha$ is the activity factor, the fraction of nodes that switch per clock cycle;
• $C_L$ is the total switched capacitance;
• $V_{DD}$ is the supply voltage;
• $f$ is the clock frequency.

Power scales with the square of voltage. At the same frequency, a 10 % lower voltage cuts dynamic power by 19 %, since $0.9^2 = 0.81$. That is why undervolting a card, where its silicon allows it, saves so much power.

Why higher clocks need higher voltage

Each logic gate takes a finite time to switch, its propagation delay $t_{pd}$. Within one clock period the signal must pass through the slowest chain of gates (the critical path) and settle before the next clock edge, with time to spare for the flip-flop's setup time $t_{\text{setup}}$ and the clock skew $t_{\text{skew}}$:

$$f_{\max} \approx \frac{1}{t_{pd,\text{crit}} + t_{\text{setup}} + t_{\text{skew}}} .$$

If the signal arrives late, the flip-flop can capture a wrong value: a timing error, and the computation is wrong.

A higher supply voltage drives more current through each transistor. In a simple model, the drain current grows as $(V_{GS} - V_{th})^{\beta}$, with $\beta$ between 1 and 2 for modern transistors. More current charges each node faster, $t_{pd}$ falls, and the chip can run at a higher $f$. That is the V/F curve: each step up in frequency needs a step up in voltage. The firmware stores it as a table of voltage and frequency points.

Silicon binning and process variation

Why two cards of the same model clock differently

Manufacturing is not perfectly uniform. Lithography, doping, etching and deposition all vary slightly across a wafer, so transistors on different dies end up with slightly different threshold voltages $V_{th}$, oxide thicknesses and channel lengths.

A die whose transistors switch faster at a given voltage reaches a given frequency with less voltage: a "good bin". A slower die needs more. The boost algorithm uses whatever headroom a chip has. It picks the highest point on the chip's V/F curve that stays within all of the card's limits, so a good chip on a well-cooled board runs at higher clocks than a weaker chip of the same model.

That is why the clock of a single card, on its own, says little. It has to be compared with cards of the same model and board, measured the same way, which is what fleet cohorts are for (Fleet Statistics).

Power, current and temperature limits

The boost algorithm works under several limits at once:

• Total board power (TGP): the power budget for the whole card, set in its firmware. For example, an RTX 4090's stock limit is 450 W.
• Current limits for the voltage regulator, which protect the power stages independently of total power.
• A temperature limit: above it, the card lowers its V/F point to produce less heat.

Whichever limit is reached first sets the clock. A well-cooled card usually runs into its power limit. A card with a poor thermal interface or failing fans can hit its temperature limit first and clock lower than the power budget would allow. The thermal side of this is covered in Hotspot Delta and TIM Pump-Out.

Electromigration: how heat and current wear out wiring

The mechanism

The wiring inside a die is made of metal lines only nanometres wide, carrying very high current densities. The flowing electrons transfer momentum to the metal atoms and slowly push them along. Over thousands of hours this produces two kinds of damage:

1. Voids, where atoms have been carried away. Local resistance rises until the line can open completely.
2. Hillocks, where atoms pile up. They can grow until they short to a neighbouring line.

Black's equation

The median time to failure from electromigration is modelled by Black's equation:

$$\mathrm{MTF} = A\, J^{-n}\, e^{E_a / (k_B T)} ,$$

where:

• $A$ is a constant that depends on the process;
• $J$ is the current density;
• $n$ is the current-density exponent, typically 1–2;
• $E_a$ is the activation energy;
• $k_B$ is Boltzmann's constant;
• $T$ is the absolute temperature.

The exponential makes lifetime very sensitive to temperature. With $E_a = 0.9$ eV, going from 70 °C (343 K) to 100 °C (373 K) at the same current density shortens the modelled lifetime by a factor of about 12:

$$\exp\!\left[\frac{E_a}{k_B}\left(\frac{1}{343} - \frac{1}{373}\right)\right] \approx 11.6 .$$

So sustained high temperature and high current, from long heavy overclocking or poor cooling, use up a chip's lifetime faster.

What it does and does not show

In principle, wiring whose resistance has crept up needs more voltage for the same speed, so a worn chip's V/F curve shifts. In practice, the shift on any one card is small, and without a reference for that exact chip there is nothing to measure it against. An Assurd certificate makes no claim about electromigration in a particular card.

The voltage regulator

The synchronous buck converter

The voltage regulator (VRM) converts the 12 V input from the PCIe slot and power connectors to the roughly 0.7–1.1 V the GPU core needs. It does this with synchronous buck converters:

1. The high-side switch $Q_H$ connects the 12 V input to the inductor $L$ for part of each switching cycle, the duty cycle $D$.
2. The low-side switch $Q_L$ carries the inductor current for the rest of the cycle.
3. The output capacitors $C_{\text{out}}$ smooth the inductor's ripple current into a steady output voltage.

The output voltage is set by the duty cycle:

$$V_{\text{out}} = D\, V_{\text{in}} = \frac{t_{\text{on}}}{T_{\text{sw}}}\, V_{\text{in}} .$$

For a 1.0 V core from a 12 V input, $D = 1.0 / 12 \approx 0.083$: the high-side switch conducts for only about 8 % of each cycle.

Multi-phase operation

A GPU core draws a very large current at a very low voltage: 300 W at 1.0 V is 300 A. No single converter handles that comfortably, so the core rail is fed by several identical phases in parallel, their switching cycles staggered evenly. Each phase carries a share of the current, their ripple currents partly cancel, and the regulator can respond faster to sudden changes in load.

Load line

Most GPU regulators use a load line (also called droop or adaptive voltage positioning). The output voltage is set slightly high at light load and allowed to fall in proportion to the current:

$$V_{\text{out}}(I) = V_{\text{set}} - R_{LL}\, I_{\text{load}} ,$$

where $R_{LL}$ is the load-line resistance. When the load suddenly drops, the voltage then overshoots less, which lets the regulator run with smaller margins.

What an Assurd certificate records

The physics above explains the clock and power figures on a certificate. The certificate itself records what the SOP measures:

• Peak effective clock and peak board power over the 1800 s load trace, from the HWiNFO log parsed by the server, and their ratio, clock per watt in MHz/W (Fleet Statistics).
• Thermal behaviour under load, including the hotspot delta (Hotspot Delta and TIM Pump-Out).
• Rail-to-ground resistance of the regulator's output rails before power-on, which catches dead shorts and gross partial shorts (Rail-to-Ground Resistance).
• The VBIOS registry lookup: whether the firmware exactly matches a factory image for this board (VBIOS SPI Dumps, Hashing and Silicon Identity).

The certificate does not contain any of the following:

• a readout of the card's V/F curve, or a comparison with a reference curve;
• a measurement of regulator output ripple, per-phase current or load line;
• a clock-stretching test;
• a measure of electromigration or remaining lifetime;
• detection of modified firmware.

Those would need instruments, references or tests that the SOP does not include, so we do not claim them.

Notation

Symbol	Meaning	Unit
$P_{\text{dyn}}$	Dynamic power	W
$\alpha$	Activity factor	—
$C_L$	Switched capacitance	F
$V_{DD}$	Supply voltage	V
$f$, $f_{\max}$	Clock frequency; highest reliable frequency	Hz
$t_{pd}$	Propagation delay	s
$V_{th}$	Transistor threshold voltage	V
MTF, $J$, $E_a$	Time to failure, current density, activation energy	h, A/cm², eV
$T$	Absolute temperature	K
$D$	Buck converter duty cycle	—
$R_{LL}$	Load-line resistance	Ω